Open-source
Silicon IP
for everyone.
OpenCoreLabsX engineers tapeout-ready, UVM-verified IP Cores for modern SoC, MCU, and RISC-V architectures. Our cores ship with complete documentation, 100% functional coverage, and zero licensing fees.
Four production-grade IP Cores.
Each core is designed for seamless plug-and-play integration into AMBA-based SoC and MCU architectures. All shipped with complete UVM testbenches and datasheets.
Full-duplex Universal Synchronous/Asynchronous Receiver Transmitter. Configurable baud rate via programmable divisor, parity modes (None/Even/Odd), 1–2 stop bits, 16-byte Tx/Rx FIFO, and interrupt generation. APB3 slave interface.
32-bit up/down counter with programmable period, PWM output, and compare-match interrupt. Prescaler support for wide frequency range.
I2C Master/Slave controller supporting Standard (100 kHz) and Fast (400 kHz) modes. Multi-master arbitration, START/STOP/REPEATED-START generation.
Quad-SPI Flash Controller with Execute-in-Place (XIP) mode. Full AXI4 master/slave, DMA-capable, configurable clock divider for NOR Flash compatibility.
From specification
to silicon-ready.
We follow a rigorous, coverage-driven design and verification workflow. Every IP Core undergoes the same disciplined six-stage process to guarantee tapeout-quality deliverables.
Industry-standard tools.
Open silicon, visualized.
A richer set of OpenCoreLabsX visuals for logic gates, SoC architecture, verification, and silicon implementation.
Ready to integrate?
All IP Cores are free to use, modify, and commercialize under the MIT License. No registration, no fees, no waiting. Clone and ship.