IP Core Portfolio

Tapeout-ready silicon IP.
Zero licensing fees.

Every core is synthesizable SystemVerilog, UVM-verified to 100% functional coverage, AMBA-compliant, and shipped with datasheets and integration guides.

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APBSystemVerilogUVM Verified

apb-usart-core

Full-duplex USART with configurable baud rate via programmable divisor register. Supports parity modes (None/Even/Odd), 1–2 stop bits, 16-byte Tx/Rx FIFO, and configurable interrupt generation. APB3 slave interface with standard 32-bit register map.

Bus Interface
AMBA APB3
FIFO Depth
16 bytes Tx/Rx
Coverage
100% Functional
License
MIT
View Repository
APB USART RTL Design
APB Timer Core logic visualization
APB · SV
02 / APB Timer
apb-timer-core

32-bit programmable timer with PWM, prescaler, and compare-match interrupt. Configurable up/down counting mode.

100% Coverage
APB I2C Core SoC integration visualization
APB · SV
03 / APB I2C
apb-i2c-core

I2C Master/Slave supporting 100 kHz and 400 kHz modes. Multi-master arbitration and full START/STOP/RESTART control.

100% Coverage
AXI QSPI Controller security and interface IP visualization
AXI4 · SV
04 / AXI QSPI
axi-qspi-controller

High-performance Quad-SPI controller with XIP mode. AXI4 master/slave, DMA support, configurable clock divider.

100% Coverage