Building the future of
open-source silicon.
OpenCoreLabsX was founded in early 2025 by a team of Vietnamese hardware engineers with a singular mission: to produce open-source IP Cores that match the quality of commercial offerings — at zero cost to the community.
Started in a university lab,
shipped to the world.
We started as a two-person team collaborating on a university SoC project in Ho Chi Minh City in late 2024. Frustrated by the lack of well-verified, well-documented open-source peripherals, we decided to build our own — and release them for free.
In January 2025, OpenCoreLabsX was formally established as an open-source hardware organization on GitHub. Within six months, we had shipped four production-grade IP Cores, each verified to 100% functional coverage using industrial UVM methodology.
Our cores have since been integrated into student and research SoC projects across Vietnam and beyond. Every line of RTL, every testbench, every documentation page is public, free, and forever MIT-licensed.
How we build hardware.
Six non-negotiable principles that guide every IP Core we design.
UVM testbench architecture is defined before RTL development begins. Verification drives the design, ensuring correctness is built in, not bolted on.
Every RTL module is lint-clean and synthesis-ready for both FPGA and ASIC targets. No behavioral shortcuts, no simulation-only constructs in production code.
Register maps, timing diagrams, and integration guides are versioned alongside RTL in Git. If it isn't documented, the IP is not shipped.
All bus interfaces strictly follow ARM AMBA specifications — APB for peripheral-class IP, AXI4 for high-performance controllers. Interoperability is guaranteed.
MIT license. No strings attached. Use in your research SoC, student project, or commercial chip. We believe open hardware accelerates silicon innovation globally.
We actively welcome contributions, bug reports, and feature proposals through GitHub. Together, we can build a comprehensive library of open silicon.
Meet the engineers
behind the silicon.
A focused team with deep expertise in digital design and functional verification for AMBA-based SoC architectures.
Specializes in UVM testbench architecture and coverage-driven verification for AMBA peripherals. Leads the verification strategy for all OpenCoreLabsX IP Cores.
Expert in synthesizable SystemVerilog RTL design and micro-architecture. Responsible for RTL implementation and design review across all IP Cores.